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  1994 the pd75p3018 replaces the pd753017s internal mask rom with a one-time prom, and features expanded rom capacity. because the pd75p3018 supports programming by users, it is suitable for use in evaluations of systems in development stages using the pd753012, 753016, or 753017, and for use in small-scale production. the following document describes further details of the functions. please make sure to read this document before starting design. pd753017 user's manual : u11282e features compatible with pd753017 memory capacity: ? prom : 32768 x 8 bits ? ram : 1024 x 4 bits can operate in same power supply voltage as the mask version pd753017 ? v dd = 2.2 to 5.5 v lcd controller/driver ordering information part number package prom ( 8 bits) pd75p3018gc-3b9 80-pin plastic qfp (14 x 14 mm, 0.65-mm pitch) 32768 pd75p3018gk-be9 80-pin plastic tqfp (fine pitch) (12 x 12 mm, 0.5-mm pitch) 32768 caution mask-option pull-up resistors are not provided in this device. document no. u10956ej1v0ds00 (1st edition) (previous no. ip-3538) date published august 1996 p printed in japan the information in this document is subject to change without notice. pd75p3018 mos integrated circuit data sheet 4-bit single-chip microcontroller the mark shows major revised points. * ? 1994 *
pd75p3018 2 function outline item function instruction execution time ? 0.95, 1.91, 3.81, 15.3 s (main system clock: at 4.19 mhz operation) ? 0.67, 1.33, 2.67, 10.7 s (main system clock: at 6.0 mhz operation) ? 122 s (subsystem clock: at 32.768 khz operation) internal memory prom 32768 x 8 bits ram 1024 x 4 bits general-purpose register ? 4 bit-operation: 8 4 banks ? 8 bit-operation: 4 4 banks input/output port cmos input 8 on-chip pull-up resistor connection can be specified by using software: 23 cmos input/output 16 cmos output 8 also used for segment pins n-ch open drain input/output 8 13-v breakdown voltage total 40 lcd controller/driver ? segment number selection : 24/28/32 segments (can be changed to cmos output port in 4 time-unit; max. 8) ? display mode selection : static 1/2 duty (1/2 bias) 1/3 duty (1/2 bias) 1/3 duty (1/3 bias) 1/4 duty (1/3 bias) timer 5 channels: ? 8-bit timer/event counter: 3 channels (can be used for 16-bit timer/event counter) ? basic interval timer/watchdog timer: 1 channel ? watch timer: 1 channel serial interface ? 3-wire serial i/o mode ... msb or lsb can be selected for transferring top bit ? 2-wire serial i/o mode ? sbi mode bit sequential buffer (bsb) 16 bits clock output (pcl) ? f , 524, 262, 65.5 khz (main system clock: at 4.19 mhz operation) ? f , 750, 375, 93.8 khz (main system clock: at 6.0 mhz operation) buzzer output (buz) ? 2, 4, 32 khz (main system clock: at 4.19 mhz operation or subsystem clock: at 32.768 khz operation) ? 2.86, 5.72, 45.8 khz (main system clock: at 6.0 mhz operation) vectored interrupts ? external : 3 ? internal : 5 test input ? external : 1 ? internal : 1 system clock oscillator ? ceramic or crystal oscillator for main system clock oscillation ? crystal oscillator for subsystem clock oscillation standby function stop/halt mode power supply voltage v dd = 2.2 to 5.5 v package ? 80-pin plastic qfp (14 x 14 mm) ? 80-pin plastic tqfp (fine pitch) (12 x 12 mm) * *
pd75p3018 3 contents 1. pin configuration (top view) .................................................................................................. 4 2. block diagram ........................................................................................................................... 5 3. pin functions .............................................................................................................................. 6 3.1 port pins .................................................................................................................................................... 6 3.2 non-port pins ............................................................................................................................................ 8 3.3 pin input/output circuits .......................................................................................................................... 10 3.4 recommended connection for unused pins ......................................................................................... 12 4. switching function between mk i and mk ii mode .......................................................... 13 4.1 difference between mk i mode and mk ii mode ...................................................................................... 13 4.2 setting of stack bank selection register (sbs) .................................................................................... 14 5. differences between pd75p3018 and pd753012, 753016, and 753017....................... 15 6. memory configuration ........................................................................................................... 16 7. instruction set .......................................................................................................................... 20 8. one-time prom (program memory) write and verify ................................................... 30 8.1 operation modes for program memory write/verify ............................................................................. 30 8.2 program memory write procedure .......................................................................................................... 31 8.3 program memory read procedure .......................................................................................................... 32 8.4 one-time prom screening ...................................................................................................................... 33 9. electrical characteristics ................................................................................................ 34 10. package drawings ................................................................................................................... 48 11. recommended soldering conditions ................................................................................ 50 appendix a pd75316b, 753017 and 75p3018 function list ................................................... 51 appendix b development tools ................................................................................................ 53 appendix c related documents ................................................................................................ 57 * * *
pd75p3018 4 1. pin configuration (top view) ? 80-pin plastic qfp (14 14 mm) pd75p3018gc-3b9 ? 80-pin plastic tqfp (fine pitch) (12 12 mm) pd75p3018gk-be9 pin identifications p00-p03 : port0 s0-31 : segment output 0-31 p10-p13 : port1 com0-3 : common output 0-3 p20-p23 : port2 v lc0-2 : lcd power supply 0-2 p30-p33 : port3 bias : lcd power supply bias control p40-p43 : port4 lcdcl : lcd clock p50-p53 : port5 sync : lcd synchronization p60-p63 : port6 ti0-2 : timer input 0-2 p70-p73 : port7 pto0-2 : programmable timer output 0-2 bp0-bp7 : bit port 0-7 buz : buzzer clock kr0-kr7 : key return 0-7 pcl : programmable clock sck : serial clock int0, 1, 4 : external vectored interrupt 0, 1, 4 si : serial input int2 : external test input 2 so : serial output x1, 2 : main system clock oscillation 1, 2 sb0, 1 : serial bus 0,1 xt1, 2 : subsystem clock oscillation 1, 2 reset : reset v pp : programming power supply md0-md3 : mode selection 0-3 v dd : positive power supply d0-d7 : data bus 0-7 vss : ground s11 80 s10 79 s9 78 s8 77 s7 76 s6 75 s5 74 s4 73 s3 72 s2 71 s1 70 s0 69 reset 68 p73/kr7 67 p72/kr6 66 p71/kr5 65 p70/kr4 64 p63/kr3 63 p62/kr2 62 p61/kr1 61 1 s12 s13 s14 s15 2 3 4 s16 5 s17 6 s18 7 s19 8 s20 9 s21 10 s22 11 s23 12 s24/bp0 13 s25/bp1 14 s26/bp2 15 s27/bp3 16 s28/bp4 17 s29/bp5 18 s30/bp6 19 s31/bp7 20 com0 21 com1 22 com2 23 com3 24 bias 25 v lc0 26 v lc1 27 v lc2 28 p40/d0 29 p41/d1 30 p42/d2 31 p43/d3 32 vss 33 p50/d4 34 p51/d5 35 p52/d6 36 p53/d7 37 p00/int4 38 p01/sck 39 p02/so/sb0 40 60 p60/kr0 x2 x1 v pp xt2 59 58 57 56 xt1 55 v dd 54 p33/md3 53 p32/md2 52 p31/sync/md1 51 p30/lcdcl/md0 50 p23/buz 49 p22/pcl/pto2 48 p21/pto1 47 p20/pto0 46 p13/ti0 45 p12/int2/ti1/ti2 44 p11/int1 43 p10/int0 42 p03/si/sb1 41
pd75p3018 5 port0 p00 to p03 4 port1 p10 to p13 4 port2 p20 to p23 4 port3 p30 to p33 /md0 to md3 4 port4 p40/d0 to p43/d3 4 port5 p50/d4 to p53/d7 4 port6 p60 to p63 4 port7 p70 to p73 4 lcd controller /driver s0 to s23 24 s24/bp0 to s31/bp7 8 com0 to com3 4 v lc0 to v lc2 3 bias lcdcl/p30 sync/p31 f lcd v pp v dd reset v ss cpu clock f stand by control x2 x1 xt2 xt1 system clock generator main sub clock divider clock output control fx/2 n pcl/p22 general reg. ram data memory 1024 x 4 bits bank sbs sp (8) alu decode and control timer/event counter #1 pto1/p21 int1 timer/event counter #2 pto2/p22/pcl int2 basic interval timer/ watchdog timer intbt timer/event counter #0 ti0/p13 int 0 clocked serial interface si/sb1/p03 intcsi interrupt control int0/p10 ti1/ti2/ p12/int2 pto0/p20 tout0 watch timer intw buz/p23 f lcd so/sb0/p02 sck/p01 tout0 int1/p11 int2/p12 int4/p00 kr0/p60 to kr7/p73 bit seq. buffer (16) 8 program counter (15) prom program memory 32768 x 8 bits cy tout0 2. block diagram
pd75p3018 6 3. pin functions 3.1 port pins (1/2) pin name i/o shared by function 8-bit status i/o circuit i/o after reset type note 1 p00 input int4 this is a 4-bit input port (port0). input p01 to p03 are 3-bit pins for which an internal p01 i/o sck pull-up resistor connection can be specified -a by software. p02 i/o so/sb0 -b p03 i/o si/sb1 -c p10 input int0 this is a 4-bit input port (port1). input -c these are 4-bit pins for which an internal pull-up p11 int1 resistor connection can be specified by software. int0 includes noise elimination function. p12 ti1/ti2/int2 p13 ti0 p20 i/o pto0 this is a 4-bit i/o port (port2). input e-b these are 4-bit pins for which an internal pull-up p21 pto1 resistor connection can be specified by software. p22 pcl/pto2 p23 buz p30 i/o lcdcl/md0 this is a programmable 4-bit i/o port (port3). input e-b input and output in single-bit units can be specified. p31 sync/md1 when set for 4-bit units, an internal pull-up resistor connection can be specified by software. p32 md2 p33 md3 p40 note 2 i/o d0 this is an n-ch open-drain 4-bit i/o port (port4). ? high m-e when set to open-drain, voltage is 13 v. impedance p41 note 2 d1 also functions as data i/o pin (lower 4 bits) for program memory (prom) write/verify. p42 note 2 d2 p43 note 2 d3 p50 note 2 i/o d4 this is an n-ch open-drain 4-bit i/o port (port5). high m-e when set to open-drain, voltage is 13 v. impedance p51 note 2 d5 also functions as data i/o pin (upper 4 bits) for program memory (prom) write/verify. p52 note 2 d6 p53 note 2 d7 notes 1. circuit types enclosed in brackets indicate schmitt trigger input. 2. low-level input leakage current increases when input instructions or bit manipulation instructions are executed. * *
pd75p3018 7 3.1 port pins (2/2) pin name i/o shared by function 8-bit status i/o circuit i/o after reset type note 1 p60 i/o kr0 this is a programmable 4-bit i/o port (port6). ? input -a input and output in single-bit units can be specified. p61 kr1 when set for 4-bit units, an internal pull-up resistor connection can be specified by software. p62 kr2 p63 kr3 p70 i/o kr4 this is a 4-bit i/o port (port7). input -a when set for 4-bit units, an internal pull-up resistor p71 kr5 connection can be specified by software. p72 kr6 p73 kr7 bp0 output s24 1-bit i/o port (bit port). these pins are also used note 2 h-a as segment output pin. bp1 s25 bp2 s26 bp3 s27 bp4 output s28 bp5 s29 bp6 s30 bp7 s31 notes 1. circuit types enclosed in brackets indicate schmitt trigger input. 2. v lc1 is selected as the input source for bp0 to bp7. the output level varies depending on the external circuit for bp0 to bp7 and v lc1 . example: as shown below, bp0 to bp7 are mutually connected via the pd75p3018, so the output levels of bp0 to bp7 are determined by the sizes of r 1 , r 2 , and r 3 . r 1 v lc1 on on bp0 bp1 r 3 r 2 v dd pd75p3018
pd75p3018 8 3.2 non-port pins (1/2) pin name i/o shared by function status i/o circuit after reset type note ti0 input p13 external event pulse input to timer/event counter input -c ti1, ti2 input p12/int2 pto0 i/o p20 timer/event counter output input e-b pto1 p21 pto2 p22 pcl output p22 clock output input e-b buz i/o p23 frequency output (for buzzer or system clock trimming) input e-b sck i/o p01 serial clock i/o input -a so/sb0 i/o p02 serial data output input -b serial data bus i/o si/sb1 i/o p03 serial data input input -c serial data bus i/o int4 input p00 edge detection vectored interrupt input input (valid for detecting both rising and falling edges) int0 input p10 edge detection vectored interrupt input clock synch/asynch input -c (detected edge is selectable) is selectable int1 p11 asynch int2 input p12/ti1/ti2 rising edge detection test input asynch input -c kr0-kr3 i/o p60-p63 parallel falling edge detection test input input -a kr4-kr7 i/o p70-p73 parallel falling edge detection test input input -a x1 input ceramic/crystal oscillation circuit connection for main system clock. if using an external clock, input to x1 and input x2 inverted phase to x2. xt1 input crystal oscillation circuit connection for subsystem clock. if using an external clock, input to xt1 and input inverted xt2 phase to xt2. xt1 can be used as a 1-bit (test) input. reset input system reset input md0 i/o p30/lcdcl mode selection for program memory (prom) write/verify input e-b md1 p31/sync md2, md3 p32, p33 d0-d3 i/o p40-p43 data bus for program memory (prom) write/verify input m-e d4-d7 p50-p53 v pp programmable power supply voltage for program memory (prom) write/verify. for normal operation, connect directly to v dd . apply +12.5 v for prom write/verify. v dd positive power supply vss ground note circuit types enclosed in brackets indicate schmitt trigger input.
pd75p3018 9 3.2 non-port pins (2/2) pin name i/o shared by function status i/o circuit after reset type s0-s23 output segment signal output note 1 g-a s24-s31 output bp0-bp7 segment signal output note 1 h-a com0-com3 output common signal output note 1 g-b v lc0- v lc2 power source for lcd driver bias output output for external split resistor cut high impedance lcdcl note 2 i/o p30 clock output for driving external expansion driver input e-b sync note 2 i/o p31 clock output for synchronization of external expansion driver input e-b notes 1. the v lcx (x = 0, 1, 2) shown below are selected as the input source for the display outputs. s0-s31: v lc1 , com0-com2: v lc2 , com3: v lc0 2. these pins are provided for future system expansion. currently, only p30 and p31 are used.
pd75p3018 10 3.3 pin input/output circuits the input/output circuits for the pd75p3018s pins are shown in abbreviated form below. in v dd p-ch n-ch v dd p-ch n-ch out data output disable in v dd p-ch in/out p.u.r. enable data p.u.r. type d output disable p.u.r. : pull-up resistor type a v dd p-ch p.u.r. enable p.u.r. p.u.r. : pull-up resistor in v dd p-ch in/out p.u.r. enable data p.u.r. type d output disable p.u.r. : pull-up resistor type b cmos standard input buffer push-pull output that can be set to high impedance output (with both p-ch and n-ch off). schmitt trigger input with hysteresis characteristics. (continued) type a type d type e-b type b type b-c type f-a
pd75p3018 11 type f-b type h-a type m-c type g-a type g-b type m-e output disable v dd p-ch n-ch in/out data v dd p-ch p.u.r. enable p.u.r. output disable (n) output disable (p) p.u.r. : pull-up resistor in/out type g-a voltage controller type e-b seg data output disable bit port data v dd p-ch in/out p.u.r. enable data p.u.r. output disable p.u.r. : pull-up resistor n-ch p-ch out n-ch p-ch v lc0 v lc1 com data v lc2 n-ch n-ch p-ch pull-up resistor operated only when executing input instructions (when pins are low level, current flows from v dd to pins). output disable data n-ch in/out (+13-v breakdown voltage) note v dd p-ch input instruction note p.u.r. * n-ch n-ch v lc2 p-ch n-ch p-ch out v lc0 v lc1 seg data * * (+13-v breakdown voltage)
pd75p3018 12 3.4 recommended connection for unused pins pin recommended connection p00/int4 connect to v ss or v dd p01/sck connect to v ss or v dd p02/so/sb0 p03/si/sb1 connect to v ss p10/int0, p11/int1 connect to v ss or v dd p12/ti1/ti2/int2 p13/ti0 p20/pto0 input status :connect to vss or v dd through p21/pto1 individual resistor p22/pto2/pcl output status :open p23/buz p30/lcdcl/md0 p31/sync/md1 p32/md2, p33/md3 p40-p43 p50-p53 p60/kr0-p63/kr3 p70/kr4-p73/kr7 s0-s23 open s24/bp0-s31/bp7 com0-com3 v lc0 -v lc2 connect to vss bias connect to vss only when v lc0 to v lc2 are all not used. in other cases, leave open. xt1 note connect to vss xt2 note open note when subsystem clock is not used, specify sos.0 = 1 (indicates that internal feedback resistor is disconnected). *
pd75p3018 13 4. switching function between mk i and mk ii mode setting a stack bank selection (sbs) register for the pd75p3018 enables the program memory to be switched between mk i mode and mk ii mode. this function is applicable when using the pd75p3018 to evaluate the pd753012, 753016, or 753017. when the sbs bit 3 is set to 1 : sets mk i mode (supports mk i mode for pd753012, 753016, and 753017) when the sbs bit 3 is set to 0 : sets mk ii mode (supports mk ii mode for pd753012, 753016, and 753017) 4.1 difference between mk i mode and mk ii mode table 4-1 lists points of difference between the mk i mode and the mk ii mode for the pd75p3018. table 4-1. difference between mk i mode and mk ii mode item mk i mode mk ii mode program counter pc 13-0 pc 14-0 pc 14 is fixed at 0 program memory (bytes) 16384 32768 data memory (bits) 1024 x 4 stack stack bank selectable via memory banks 0 to 3 no. of stack bytes 2 bytes 3 bytes instruction bra !addr1 instruction use disabled use enabled calla !addr1 instruction instruction call !addr instruction 3 machine cycles 4 machine cycles execution time callf !faddr instruction 2 machine cycles 3 machine cycles supported mask roms when set to mk i mode: when set to mk ii mode: pd753012, 753016, and 753017 pd753012, 753016, and 753017 caution the mk ii mode supports a program area exceeding 16 kbytes for the 75x and 75xl series. therefore, this mode is effective for enhancing software compatibility with products that have a program area of more than 16 kbytes. with regard to the number of stack bytes during execution of subroutine call instructions, the usable area increases by 1 byte per stack compared to the mk i mode when the mk ii mode is selected. however, when the call !addr and callf !faddr instructions are used, the machine cycle becomes longer by 1 machine cycle. therefore, if more emphasis is placed on ram use efficiency and processing performance than on software compatibility, the mk i mode should be used. *
pd75p3018 14 4.2 setting of stack bank selection register (sbs) use the stack bank selection register to switch between mk i mode and mk ii mode. figure 4-1 shows the format for doing this. the stack bank selection register is set using a 4-bit memory manipulation instruction. when using the mk i mode, be sure to initialize the stack bank selection register to 10xxb note at the beginning of the program. when using the mk ii mode, be sure to initialize it to 00xxb note . note set the desired value for xx. figure 4-1. format of stack bank selection register cautions 1. sbs3 is set to 1 after reset input, and consequently the cpu operates in mk i mode. when using instructions for mk ii mode, set sbs3 to 0 and set mk ii mode before using the instructions. 2. when using mk ii mode, execute a subroutine call instruction and an interrupt instruction after reset input and after setting the stack bank selection register. sbs3 sbs2 sbs1 sbs0 f84h address 3 2 1 0 sbs 0 0 1 1 0 1 0 1 symbol stack area specification memory bank 0 memory bank 1 memory bank 2 memory bank 3 0 be sure to enter ? for bit 2. 0 1 mk ii mode mk i mode mode selection specification
pd75p3018 15 5. differences between pd75p3018 and pd753012, 753016, and 753017 the pd75p3018 replaces the internal mask rom in the pd753012, 753016, and 753017 with a one-time prom and features expanded rom capacity. the pd75p3018s mk i mode supports the mk i mode in the pd753012, 753016, and 753017 and the pd75p3018s mk ii mode supports the mk ii mode in the pd753012, 753016, and 753017. table 5-1 lists differences among the pd75p3018 and the pd753012, 753016, and 753017. be sure to check the differences among these products before using them with proms for debugging or prototype testing of application systems or, later, when using them with a mask rom for full-scale production. for the cpu functions and internal hardwares, refer to pd753017 user's manual (u11282e). table 5-1. differences between pd75p3018 and pd753012, 753016, and 753017 item pd753012 pd753016 pd753017 pd75p3018 program counter 14 bits 15 bits program memory (bytes) mask rom one-time prom during 12288 16384 16384 16384 mk i mode during 12288 16384 24576 32768 mk ii mode data memory (x 4 bits) 1024 mask options pull-up resistor for yes (can be specified whether to incorporate or not) no (cannot incorporate) port4 and port5 lcd split resistor feed back resistor yes (can be specified with the sos register whether to no (cannot incorporate) for subsystem clock incorporate or not) wait time yes (can be specified either 2 17 /f x or 2 15 /f x ) note no (fixed at 2 15 /f x ) note during reset pin configuration pin nos. 29 to 32 p40 to p43 p40/d0 to p43/d3 pin nos. 34 to 37 p50 to p53 p50/d4 to p53/d7 pin no. 50 p30/lcdcl p30/lcdcl/md0 pin no. 51 p31/sync p31/sync/md1 pin nos. 52 and 53 p32, p33 p32/md2, p33/md3 pin no. 57 ic v pp other noise resistance and noise radiation may differ due to the different circuit sizes and mask layouts. note for 2 17 /f x , during 6.0 mhz operation is 21.8 ms, and during 4.19 operation is 31.3 ms. for 2 15 /f x , during 6.0 mhz operation is 5.46 ms, and during 4.19 operation is 7.81 ms. caution noise resistance and noise radiation are different in prom and mask roms. in transferring to mask rom versions from the prom version in a processe between prototype development and full production, be sure to fully evaluate the mask rom versions cs (not es). * *
pd75p3018 16 6. memory configuration 6.1 program counter (pc) ... 15 bits this is a 15-bit binary counter that stores program memory address data. bit 15 is valid during mk ii mode. but pc14 is fixed at zero during mk i mode, and the lower 14 bits are all valid. figure 6-1. configuration of program counter 6.2 program memory (prom) ... 32768 x 8 bits the program memory consists of 32768 x 8-bit one-time prom. the program memory address can be selected as shown below by setting the stack bank selection (sbs) register. mk i mode mk ii mode usable address 0000h to 3fffh 0000h to 7fffh figures 6-2 and 6-3 show the addressing ranges for the program memory and branch instruction and the subroutine call instruction, during mk i and mk ii modes. pc14 pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 pc fixed at zero during mk i mode
pd75p3018 17 figure 6-2. program memory map (mk i mode) mbe mbe mbe mbe mbe mbe mbe rbe rbe rbe rbe rbe rbe rbe internal reset start address (upper 6 bits) internal reset start address (lower 8 bits) intbt/int4 start address (upper 6 bits) intbt/int4 start address (lower 8 bits) int0 start address (upper 6 bits) int0 start address (lower 8 bits) int1 start address (upper 6 bits) int1 start address (lower 8 bits) intcsi start address (upper 6 bits) intcsi start address (lower 8 bits) intt0 start address (upper 6 bits) intt0 start address (lower 8 bits) intt1, intt2 start address (upper 6 bits) intt1, intt2 start address (lower 8 bits) reference table for geti instruction 0000h 0002h 0004h 0006h 0008h 000ah 000ch 007fh 0080h 07ffh 0800h 0fffh 1000h 1fffh 2000h 2fffh 3000h 3fffh callf !faddr instruction entry address ?br bcde instruction ?br bcxa instruction ?br !addr instruction ?call !addr instruction branch address branch/call address by geti br $addr instruction relative branch address (?5 to ?, +2 to +16) brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address 765 0 0020h remark for instructions other than those noted above, the br pcde and br pcxa instructions can be used to branch to addresses with changes in the pcs lower 8 bits only.
pd75p3018 18 figure 6-3. program memory map (mk ii mode) caution to allow the vectored interrupts 14-bit start address (noted above), set the address within a 16-k area (0000h to 3fffh). remark for instructions other than those noted above, the br pcde and br pcxa instructions can be used to branch to addresses with changes in the pcs lower 8 bits only. mbe mbe mbe mbe mbe mbe mbe rbe rbe rbe rbe rbe rbe rbe internal reset start address (upper 6 bits) internal reset start address (lower 8 bits) intbt/int4 start address (upper 6 bits) intbt/int4 start address (lower 8 bits) int0 start address (upper 6 bits) int0 start address (lower 8 bits) int1 start address (upper 6 bits) int1 start address (lower 8 bits) intcsi start address (upper 6 bits) intcsi start address (lower 8 bits) intt0 start address (upper 6 bits) intt0 start address (lower 8 bits) intt1, intt2 start address (upper 6 bits) intt1, intt2 start address (lower 8 bits) reference table for geti instruction 0000h 0002h 0004h 0006h 0008h 000ah 000ch 1fffh 2000h 2fffh 3000h 3fffh 4000h 4fffh 5000h 5fffh 6000h 6fffh 7000h 7fffh 0020h 007fh 0080h 07ffh 0800h 0fffh 1000h callf !faddr instruction entry address br !addr instruction branch address call !addr instruction branch address branch/call address by geti brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address 765 0 brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address branch addresses for the following instructions ?br bcde ?br bcxa ?bra !addr1 ?calla !addr1 br $addr1 instruction relative branch address (?5 to ?, +2 to +16)
pd75p3018 19 6.3 data memory (ram) ... 1024 x 4 bits figure 6-4 shows the data memory configuration. data memory consists of a data area and a peripheral hardware area. the data area consists of 1024 x 4-bit static ram. figure 6-4. data memory map note memory bank 0, 1, 2, or 3 can be selected as the stack area. (8 x 4) 256 x 4 (248 x 4) 256 x 4 (224 x 4) (32 x 4) 256 x 4 256 x 4 128 x 4 0 1 2 3 15 000h 01fh 020h 0ffh 100h 1dfh 1e0h 1ffh 200h 2ffh 300h 3ffh f80h fffh general-purpose register area display data memory data area static ram (1024 x 4) stack area note peripheral hardware area data memory memory bank not incorporated
pd75p3018 20 7. instruction set (1) representation and coding formats for operands in the instructions operand area, use the following coding format to describe operands corresponding to the instructions operand representations (for further description, see the ra75x assembler package users manual Clanguage (eeu- 1363) ). when there are several codes, select and use just one. codes that consist of upper-case letters and + or C symbols are key words that should be entered as they are. for immediate data, enter an appropriate numerical value or label. enter register flag symbols as label descriptors instead of mem, fmem, pmem, bit, etc. (for details, refer to the user's manual ). the number of labels that can be entered for fmem and pmem are restricted. representation coding format reg x, a, b, c, d, e, h, l reg1 x, b, c, d, e, h, l rp xa, bc, de, hl rp1 bc, de, hl rp2 bc, de rp xa, bc, de, hl, xa, bc, de, hl rp1 bc, de, hl, xa, bc, de, hl rpa hl, hl+, hlC, de, dl rpa1 de, dl n4 4-bit immediate data or label n8 8-bit immediate data or label mem 8-bit immediate data or label note bit 2-bit immediate data or label fmem fb0h-fbfh, ff0h-fffh immediate data or label pmem fc0h-fffh immediate data or label addr 0000h-3fffh immediate data or label (mk i mode and mk ii mode) addr1 0000h-7fffh immediate data or label (mk ii mode only) caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20h-7fh immediate data (however, bit0 = 0) or label portn port0-port7 iexxx iebt, iecsi, iet0, iet1, iet2, ie0-ie2, ie4, iew rbn rb0-rb3 mbn mb0-mb3, mb15 note when processing 8-bit data, only even-numbered addresses can be specified.
pd75p3018 21 (2) operation legend a : a register; 4-bit accumulator b : b register c : c register d : d register e : e register h : h register l : l register x : x register xa : register pair (xa); 8-bit accumulator bc : register pair (bc) de : register pair (de) hl : register pair (hl) xa : expansion register pair (xa) bc : expansion register pair (bc) de : expansion register pair (de) hl : expansion register pair (hl) pc : program counter sp : stack pointer cy : carry flag; bit accumulator psw : program status word mbe : memory bank enable flag rbe : register bank enable flag portn : port n (n = 0 to 7) ime : interrupt master enable flag ips : interrupt priority selection register iexxx : interrupt enable flag rbs : register bank selection register mbs : memory bank selection register pcc : processor clock control register . : delimiter for address and bit (xx) : addressed data xxh : hexadecimal data
pd75p3018 22 (3) description of symbols used in addressing area remarks 1. mb indicates access-enabled memory banks. 2. in area *2, mb = 0 for both mbe and mbs. 3. in areas *4 and *5, mb = 15 for both mbe and mbs. 4. areas *6 to *11 indicate corresponding address-enabled areas. mb = 0 (000h-07fh) mb = 15 (f80h-fffh) mb = mbs mbs = 0-3, 15 mb = mbe ?mbs mbs = 0-3, 15 *1 mb = 0 *2 mbe = 1 : mbe = 0 : *3 mb = 15, fmem = fb0h-fbfh, ff0h-fffh mb = 15, pmem = fc0h-fffh addr = 0000h-3fffh *4 *5 *6 addr, addr1 = *7 (current pc) ?5 to (current pc) ? (current pc) +2 to (current pc) +16 *8 caddr = 0000h-0fffh (pc 14 , 13 , 12 = 000b: mk i or mk ii mode) or 1000h-1fffh (pc 14 , 13 , 12 = 001b: mk i or mk ii mode) or 2000h-2fffh (pc 14 , 13 , 12 = 010b: mk i or mk ii mode) or 3000h-3fffh (pc 14 , 13 , 12 = 011b: mk i or mk ii mode) or 4000h-4fffh (pc 14 , 13 , 12 = 100b: mk ii mode) or 5000h-5fffh (pc 14 , 13 , 12 = 101b: mk ii mode) or 6000h-6fffh (pc 14 , 13 , 12 = 110b: mk ii mode) or 7000h-7f7fh (pc 14 , 13 , 12 = 111b: mk ii mode) faddr = 0000h-07ffh taddr = 0020h-007fh addr1 = 0000h-7fffh (mk ii mode only) *9 *10 *11 program memory addressing data memory addressing
pd75p3018 23 (4) description of machine cycles s indicates the number of machine cycles required for skipping of skip-specified instructions. the value of s varies as shown below. ? no skip ..................................................................... s = 0 ? skipped instruction is 1-byte or 2-byte instruction .... s = 1 ? skipped instruction is 3-byte instruction note .............. s = 2 note 3-byte instructions: br !addr, bra !addr1, call !addr, calla !addr1 caution the geti instruction is skipped for one machine cycle. one machine cycle equals one cycle (= t cy ) of the cpu clock f . use the pcc setting to select among four cycle times.
pd75p3018 24 instruction mnemonic operand no. of machine operation addressing skip group bytes cycle area condition transfer mov a, #n4 1 1 a<-n4 string-effect a reg1, #n4 2 2 reg1<-n4 xa, #n8 2 2 xa<-n8 string-effect a hl, #n8 2 2 hl<-n8 string-effect b rp2, #n8 2 2 rp2<-n8 a, @hl 1 1 a<-(hl) *1 a, @hl+ 1 2+s a<-(hl), then l<-l+1 *1 l=0 a, @hlC 1 2+s a<-(hl), then l<-lC1 *1 l=fh a, @rpa1 1 1 a<-(rpa1) *2 xa, @hl 2 2 xa<-(hl) *1 @hl, a 1 1 (hl)<-a *1 @hl, xa 2 2 (hl)<-xa *1 a, mem 2 2 a<-(mem) *3 xa, mem 2 2 xa<-(mem) *3 mem, a 2 2 (mem)<-a *3 mem, xa 2 2 (mem)<-xa *3 a, reg1 2 2 a<-reg1 xa, rp 2 2 xa<-rp reg1, a 2 2 reg1<-a rp1, xa 2 2 rp1<-xa xch a, @hl 1 1 a<->(hl) *1 a, @hl+ 1 2+s a<->(hl), then l<-l+1 *1 l=0 a, @hlC 1 2+s a<->(hl), then l<-lC1 *1 l=fh a, @rpa1 1 1 a<->(rpa1) *2 xa, @hl 2 2 xa<->(hl) *1 a, mem 2 2 a<->(mem) *3 xa, mem 2 2 xa<->(mem) *3 a, reg1 1 1 a<->reg1 xa, rp 2 2 xa<->rp table movt xa, @pcde 1 3 xa<-(pc 13-8 +de) rom reference xa, @pcxa 1 3 xa<-(pc 13-8 +xa) rom xa, @bcde 1 3 xa<-(bcde) rom note *11 xa, @bcxa 1 3 xa<-(bcxa) rom note *11 note only the lower 3 bits in the b register are valid.
pd75p3018 25 instruction mnemonic operand no. of machine operation addressing skip group bytes cycle area condition bit transfer mov1 cy, fmem.bit 2 2 cy<-(fmem.bit) *4 cy, pmem.@l 2 2 cy<-(pmem 7-2 +l 3-2 .bit(l 1-0 )) *5 cy, @h+mem.bit 2 2 cy<-(h+mem 3-0 .bit) *1 fmem.bit, cy 2 2 (fmem.bit)<-cy *4 pmem.@l, cy 2 2 (pmem 7-2 +l 3-2 .bit(l 1-0 ))<-cy *5 @h+mem.bit, cy 2 2 (h+mem 3-0 .bit)<-cy *1 arithmetic adds a, #n4 1 1+s a<-a+n4 carry xa, #n8 2 2+s xa<-xa+n8 carry a, @hl 1 1+s a<-a+(hl) *1 carry xa, rp 2 2+s xa<-xa+rp carry rp1, xa 2 2+s rp1<-rp1+xa carry addc a, @hl 1 1 a, cy<-a+(hl)+cy *1 xa, rp 2 2 xa, cy<-xa+rp+cy rp1, xa 2 2 rp1, cy<-rp1+xa+cy subs a, @hl 1 1+s a<-aC(hl) *1 borrow xa, rp 2 2+s xa<-xaCrp borrow rp1, xa 2 2+s rp1<-rp1Cxa borrow subc a, @hl 1 1 a, cy<-aC(hl)Ccy *1 xa, rp 2 2 xa, cy<-xaCrpCcy rp1, xa 2 2 rp1, cy<-rp1CxaCcy and a, #n4 2 2 a<-a ^ n4 a, @hl 1 1 a<-a ^ (hl) *1 xa, rp 2 2 xa<-xa ^ rp rp1, xa 2 2 rp1<-rp1 ^ xa or a, #n4 2 2 a<-avn4 a, @hl 1 1 a<-av(hl) *1 xa, rp 2 2 xa<-xavrp rp1, xa 2 2 rp1<-rp1vxa xor a, #n4 2 2 a<-av n4 a, @hl 1 1 a<-av (hl) *1 xa, rp 2 2 xa<-xav rp rp1, xa 2 2 rp1<-rp1v xa accumulator rorc a 1 1 cy<-a 0 , a 3 <-cy, a n-1 <-a n manipulation not a 2 2 a<-a increment/ incs reg 1 1+s reg<-reg+1 reg=0 decrement rp1 1 1+s rp1<-rp1+1 rp1=00h @hl 2 2+s (hl)<-(hl)+1 *1 (hl)=0 mem 2 2+s (mem)<-(mem)+1 *3 (mem)=0 decs reg 1 1+s reg<-regC1 reg=fh rp 2 2+s rp<-rpC1 rp=ffh
pd75p3018 26 instruction mnemonic operand no. of machine operation addressing skip group bytes cycle area condition comparison ske reg, #n4 2 2+s skip if reg=n4 reg=n4 @hl, #n4 2 2+s skip if (hl)=n4 *1 (hl)=n4 a, @hl 1 1+s skip if a=(hl) *1 a=(hl) xa, @hl 2 2+s skip if xa=(hl) *1 xa=(hl) a, reg 2 2+s skip if a=reg a=reg xa, rp 2 2+s skip if xa=rp xa=rp carry flag set1 cy 1 1 cy<-1 manipulation clr1 cy 1 1 cy<-0 skt cy 1 1+s skip if cy=1 cy=1 not1 cy 1 1 cy<-cy memory bit set1 mem.bit 2 2 (mem.bit)<-1 *3 manipulation fmem.bit 2 2 (fmem.bit)<-1 *4 pmem.@l 2 2 (pmem 7-2 +l 3-2 .bit(l 1-0 ))<-1 *5 @h+mem.bit 2 2 (h+mem 3-0 .bit)<-1 *1 clr1 mem.bit 2 2 (mem.bit)<-0 *3 fmem.bit 2 2 (fmem.bit)<-0 *4 pmem.@l 2 2 (pmem 7-2 +l 3-2 .bit(l 1-0 ))<-0 *5 @h+mem.bit 2 2 (h+mem 3-0 .bit)<-0 *1 skt mem.bit 2 2+s skip if(mem.bit)=1 *3 (mem.bit)=1 fmem.bit 2 2+s skip if(fmem.bit)=1 *4 (fmem.bit)=1 pmem.@l 2 2+s skip if(pmem 7-2 +l 3-2 .bit(l 1-0 ))=1 *5 (pmem.@l)=1 @h+mem.bit 2 2+s skip if(h+mem 3-0 .bit)=1 *1 (@h+mem.bit)=1 skf mem.bit 2 2+s skip if(mem.bit)=0 *3 (mem.bit)=0 fmem.bit 2 2+s skip if(fmem.bit)=0 *4 (fmem.bit)=0 pmem.@l 2 2+s skip if(pmem 7-2 +l 3-2 .bit(l 1-0 ))=0 *5 (pmem.@l)=0 @h+mem.bit 2 2+s skip if(h+mem 3-0 .bit)=0 *1 (@h+mem.bit)=0 sktclr fmem.bit 2 2+s skip if(fmem.bit)=1 and clear *4 (fmem.bit)=1 pmem.@l 2 2+s skip if(pmem 7-2 +l 3-2 .bit (l 1-0 ))=1 and clear *5 (pmem.@l)=1 @h+mem.bit 2 2+s skip if(h+mem 3-0 .bit)=1 and clear *1 (@h+mem.bit)=1 and1 cy, fmem.bit 2 2 cy<-cy ^ (fmem.bit) *4 cy, pmem.@l 2 2 cy<-cy ^ (pmem 7-2 +l 3-2 .bit(l 1-0 )) *5 cy, @h+mem.bit 2 2 cy<-cy ^ (h+mem 3-0 .bit) *1 or1 cy, fmem.bit 2 2 cy<-cyv(fmem.bit) *4 cy, pmem.@l 2 2 cy<-cyv(pmem 7-2 +l 3-2 .bit(l 1-0 )) *5 cy, @h+mem.bit 2 2 cy<-cyv(h+mem 3-0 .bit) *1 xor1 cy, fmem.bit 2 2 cy<-cyv (fmem.bit) *4 cy, pmem.@l 2 2 cy<-cyv (pmem 7-2 +l 3-2 .bit(l 1-0 )) *5 cy, @h+mem.bit 2 2 cy<-cyv (h+mem 3-0 .bit) *1
pd75p3018 27 instruction mnemonic operand no. of machine operation addressing skip group bytes cycle area condition branch br note 1 addr pc 14 <-0, pc 13-0 <-addr *6 use the assembler to select the most appropriate instruction among the following. ? br !addr ? brcb !caddr ? br $addr addr1 pc 14-0 <-addr1 *11 use the assembler to select the most appropriate instruction among the following. ? bra !addr1 ? br !addr ? brcb !caddr ? br $addr1 !addr 3 3 pc 14 <-0, pc 13-0 <-addr *6 $addr 1 2 pc 14 <-0, pc 13-0 <-addr *7 $addr1 1 2 pc 14 <-0, pc 13-0 <-addr1 pc 14-0 <-addr1 pcde 2 3 pc 14 <-0, pc 13-0 <-pc 13-8 +de pc 14-0 <-pc 14-8 +de pcxa 2 3 pc 14 <-0, pc 13-0 <-pc 13-8 +xa pc 14-0 <-pc 14-8 +xa bcde 2 3 pc 14 <-0, pc 13-0 <-bcde note 2 *11 pc 14-0 <-bcde note 2 bcxa 2 3 pc 14 <-0, pc 13-0 <-bcxa note 2 *11 pc 14-0 <-bcxa note 2 bra note 1 !addr1 3 3 pc 14-0 <-addr1 *11 brcb !caddr 2 2 pc 14 <-0, pc 13-0 <-pc 13, 12 +caddr 11-0 *8 pc 14-0 <-pc 14, 13, 12 +caddr 11-0 notes 1. shaded areas indicate support for mk ii mode only. 2. the only following bits are valid in the b register. for mk i mode : lower 2 bits for mk ii mode : lower 3 bits
pd75p3018 28 instruction mnemonic operand no. of machine operation addressing skip group bytes cycle area condition subroutine calla note !addr1 3 3 (spC5)<-0, pc 14-12 *11 stack control (spC6)(spC3)(spC4)<-pc 11-0 (spC2)<-x, x, mbe, rbe pc 14C0 <-addr1, sp<-spC6 call note !addr 3 3 (spC4)(spC1)(spC2)<-pc 11-0 *6 (spC3)<-mbe, rbe, pc 13, 12 pc 14 <-0, pc 13C0 <-addr, sp<-spC4 4 (spC5)<-0, pc 14-12 (spC6)(spC3)(spC4)<-pc 11-0 (spC2)<-x, x, mbe, rbe pc 14 <-0, pc 13-0 <-addr, sp<-spC6 callf note !faddr 2 2 (spC4)(spC1)(spC2)<-pc 11-0 *9 (spC3)<-mbe, rbe, pc 13, 12 pc 14 <-0, pc 13-0 <-000+faddr, sp<-spC4 3 (spC5)<-0, pc 14-12 (spC6)(spC3)(spC4)<-pc 11-0 (spC2)<-x, x, mbe, rbe pc 14-0 <-0000+faddr, sp<-spC6 ret note 1 3 mbe, rbe, pc 13, 12 <-(sp+1) pc 11-0 <-(sp)(sp+3)(sp+2) pc 14 <-0, sp<-sp+4 x, x, mbe, rbe<-(sp+4) 0, pc 14-12 <-(sp+1) pc 11-0 <-(sp)(sp+3)(sp+2) sp<-sp+6 rets note 1 3+s mbe, rbe, pc 13, 12 <-(sp+1) unconditional pc 11-0 <-(sp)(sp+3)(sp+2) pc 14 <-0, sp<-sp+4 then skip unconditionally x, x, mbe, rbe<-(sp+4) 0, pc 14-12 <-(sp+1) pc 11-0 <-(sp)(sp+3)(sp+2) sp<-sp+6 then skip unconditionally reti note 13pc 13, 12 <-(sp+1) 1, 0 , pc 14 <-0 pc 11-0 <-(sp)(sp+3)(sp+2) psw<-(sp+4)(sp+5), sp<-sp+6 0, pc 14-12 <-(sp+1) pc 11-0 <-(sp)(sp+3)(sp+2) psw<-(sp+4)(sp+5), sp<-sp+6 note shaded areas indicate support for mk ii mode only. other areas indicate support for mk i mode only.
pd75p3018 29 instruction mnemonic operand no. of machine operation addressing skip group bytes cycle area condition subroutine push rp 1 1 (spC1)(spC2)<-rp, sp<-spC2 stack control bs 2 2 (spC1)<-mbs, (spC2)<-rbs, sp<-spC2 pop rp 1 1 rp<-(sp+1)(sp), sp<-sp+2 bs 2 2 mbs<-(sp+1), rbs<-(sp), sp<-sp+2 interrupt ei 2 2 ime(ips.3)<-1 control iexxx 2 2 iexxx<-1 di 2 2 ime(ips.3)<-0 iexxx 2 2 iexxx<-0 i/o in note 1 a, portn 2 2 a<-portn (n=0-7) xa, portn 2 2 xa<-portn+ 1 , portn (n=4, 6) out note 1 portn, a 2 2 portn<-a (n=2-7) portn, xa 2 2 portn+ 1 , portn<-xa (n=4, 6) cpu control halt 2 2 set halt mode(pcc.2<-1) stop 2 2 set stop mode(pcc.3<-1) nop 1 1 no operation special sel rbn 2 2 rbs<-n (n=0-3) mbn 2 2 mbs<-n (n=0-3, 15) geti note 2, 3 taddr 1 3 ? when using tbr instruction *10 pc 13-0 <-(taddr) 5-0 +(taddr+1), pc 14 <-0 ? when using tcall instruction (spC4)(spC1)(spC2)<-pc 11-0 (spC3)<-mbe, rbe, pc 13, 12 , pc 14 <-0 pc 13-0 <-(taddr) 5-0 +(taddr+1) sp<-spC4 ? when using instruction other than determined by tbr or tcall referenced execute (taddr)(taddr+1) instructions instruction 1 3 ? when using tbr instruction *10 pc 13-0 <-(taddr) 5-0 +(taddr+1), pc 14 <-0 4 ? when using tcall instruction (spC5)<-0, pc 14-12 (spC6)(spC3)(spC4)<-pc 11-0 (spC2)<-x, x, mbe, rbe, pc 14 <-0 pc 13-0 <-(taddr) 5-0 +(taddr+1) sp<-spC6 3 ? when using instruction other than determined by tbr or tcall referenced execute (taddr)(taddr+1) instructions instruction notes 1. before executing the in or out instruction, set mbe to 0 or 1 and set mbs to 15. 2. tbr and tcall are assembler pseudo-instructions for the geti instructions table definitions. 3. shaded areas indicate support for mk ii mode only. other areas indicate support for mk i mode only. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
pd75p3018 30 8. one-time prom (program memory) write and verify the program memory contained in the pd75p3018 is a 32768 x 8-bit one-time prom that can be electrically written one time only. the pins listed in the table below are used for this proms write/verify operations. clock input from the x1 pin is used instead of address input as a method for updating addresses. pin function v pp pin where program voltage is applied during program memory write/verify (usually v dd potential) x1, x2 clock input pins for address updating during program memory write/verify. input the x1 pins inverted signal to the x2 pin. md0-md3 operation mode selection pin for program memory write/verify d0/p40 to d3/p43 8-bit data i/o pins for program memory write/verify (lower 4 bits) d4/p50 to d7/p53 (upper 4 bits) v dd pin where power supply voltage is applied. applies v dd = 2.2 to 5.5 v in normal operation mode and +6 v for program memory write/verify. caution pins not used for program memory write/verify should be connected to vss. 8.1 operation modes for program memory write/verify when +6 v is applied to the v dd pin and +12.5 v to the v pp pin, the pd75p3018 enters the program memory write/verify mode. the following operation modes can be specified by setting pins md0 to md3 as shown below. operation mode specification operation mode v pp v dd md0 md1 md2 md3 +12.5 v +6 v h l h l zero-clear program memory address l h h h write mode l l h h verify mode h x h h program inhibit mode x: l or h *
pd75p3018 31 8.2 program memory write procedure program memory can be written at high speed using the following procedure. (1) pull unused pins to vss through resistors. set the x1 pin low. (2) supply 5 v to the v dd and v pp pins. (3) wait 10 s. (4) select the zero-clear program memory address mode. (5) supply 6 v to the v dd and 12.5 v to the v pp pins. (6) select the program inhibit mode. (7) write data in the 1 ms write mode. (8) select the program inhibit mode. (9) select the verify mode. if the data is correct, go to step (10) and if not, repeat steps (7) to (9). (10) (x : number of write operations from steps (7) to (9)) x 1 ms additional write. (11) select the program inhibit mode. (12) apply four pulses to the x1 pin to increment the program memory address by one. (13) repeat steps (7) to (12) until the end address is reached. (14) select the zero-clear program memory address mode. (15) return the v dd and v pp pins back to 5 v. (16) turn off the power. the following figure shows steps (2) to (12). v pp v dd v dd + 1 v dd v pp v dd x1 d0/p40 to d3/p43 d4/p50 to d7/p53 md0 (p30) md1 (p31) md2 (p32) md3 (p33) data input data output data input x repetitions write verify additional write address increment
pd75p3018 32 8.3 program memory read procedure the pd75p3018 can read program memory contents using the following procedure. (1) pull unused pins to vss through resistors. set the x1 pin low. (2) supply 5 v to the v dd and v pp pins. (3) wait 10 s. (4) select the zero-clear program memory address mode. (5) supply 6 v to the v dd and 12.5 v to the v pp pins. (6) select the program inhibit mode. (7) select the verify mode. apply four pulses to the x1 pin. every four clock pulses will output the data stored in one address. (8) select the program inhibit mode. (9) select the zero-clear program memory address mode. (10) return the v dd and v pp pins back to 5 v. (11) turn off the power. the following figure shows steps (2) to (9). v pp v dd v dd + 1 v dd v pp v dd x1 d0/p40 to d3/p43 d4/p50 to d7/p53 md0 (p30) md2 (p32) md3 (p33) md1 (p31) ? data output data output
pd75p3018 33 8.4 one-time prom screening due to its structure, the one-time prom cannot be fully tested before shipment by nec. therefore, nec recommends that after the required data is written and the prom is stored under the temperature and time conditions shown below, the prom should be verified via a screening. storage temperature storage time 125c 24 hours
pd75p3018 34 9. electrical characteristics absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd C0.3 to +7.0 v prom supply voltage v pp C0.3 to +13.5 v input voltage v i1 other than ports 4 and 5 C0.3 to v dd + 0.3 v v i2 ports 4 and 5 (during n-ch open drain) C0.3 to +14 v output voltage v o C0.3 to v dd + 0.3 v high-level output current i oh per pin C10 ma total of all pins C30 ma low-level output current i ol per pin 30 ma total of all pins 220 ma operating ambient t a C40 to +85 c temperature storage temperature t stg C65 to +150 c caution if the absolute maximum rating of even one of the parameters is exceeded even momentarily, the quality of the product may be degraded. the absolute maximum ratings are therefore values which, when exceeded, can cause the product to be damaged. be sure that these values are never exceeded when using the product. capacitance (t a = 25 c, v dd = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c in f = 1 mhz 15 pf output capacitance c out unmeasured pins returned to 0 v 15 pf i/o capacitance c io 15 pf *
pd75p3018 35 main system clock oscillation circuit characteristics ( t a = C40 to +85 c) resonator recomended constants parameter conditions min. typ. max. unit ceramic v dd = 2.2 to 5.5 v oscillation frequency 1.0 6.0 note 2 mhz resonator ( f x ) note 1 oscillation after v dd has 4 m s stabilization time note 3 reached min. value of oscillation voltage range crystal v dd = 2.2 to 5.5 v oscillation frequency 1.0 6.0 note 2 mhz resonator ( f x ) note 1 oscillation v dd = 4.5 to 5.5 v 10 m s stabilization time note 3 30 external v dd = 1.8 to 5.5 v x1 input frequency 1.0 6.0 note 2 mhz clock (f x ) note 1 x1 input high-/ 83.3 500 ns low-level widths (t xh , t x l ) note s 1 . the oscillation frequency and x1 input frequency shown above indicate characteristics of the oscillation circuit only. for the instruction execution time, refer to ac characteristics. 2 . when the supply voltage is 1.8 v v dd < 2.7 v and the oscillation frequency is 4.19 mhz < f x 6.0 mhz, do not select processor clock control register (pcc) = 0011 as the instruction execution time. if pcc = 0011, one machine cycle is less than 0.95 s, falling short of the rated value of 0.95 s. 3 . the oscillation stabilization time is the time required for oscillation to be stabilized after v dd has been applied or stop mode has been released. cautio n when using the main system clock oscillation circuit, wire the portion enclosed in the broken line in the above figure as follows to prevent adverse influences due to wiring capacitance: ? keep the wiring length as short as possible. ? do not cross the wiring with other signal lines. ? do not route the wiring in the vicinity of a line through which a high alternating current flows. ? always keep the ground point of the capacitor of the oscillation circuit at the same potential as v dd . ? do not ground to a power supply pattern through which a high current flows. ? do not extract signals from the oscillation circuit. x1 x2 c1 c2 v dd x1 x2 c1 c2 v dd x1 x2
pd75p3018 36 subsystem clock oscillation circuit characteristics ( t a = C40 to +85 c, v dd = 2.2 to 5.5 v) resonator recomended constants parameter conditions min. typ. max. unit crystal oscillation frequency 32 32.768 35 khz resonator ( f x t ) note 1 oscillation v dd = 4.5 to 5.5 v 1.0 2 s stabilization time note 2 v dd 3 2.2 v 10 external xt1 input frequency 32 100 khz clolck ( f x t ) note 1 xt1 input high-/ 5 15 s low-level widths (t xth , t xt l ) note s 1 . the oscillation frequency and xt1 input frequency shown above indicate characteristics of the oscillation circuit only. for the instruction execution time, refer to ac characteristics. 2 . the oscillation stabilization time is the time required for oscillation to be stabilized after v dd has been applied. cautio n when using the subsystem clock oscillation circuit, wire the portion enclosed in the broken line in the above figure as follows to prevent adverse influences due to wiring capacitance: ? keep the wiring length as short as possible. ? do not cross the wiring with other signal lines. ? do not route the wiring in the vicinity of a line through which a high alternating current flows. ? always keep the ground point of the capacitor of the oscillation circuit at the same potential as v dd . ? do not ground to a power supply pattern through which a high current flows. ? do not extract signals from the oscillation circuit. the subsystem clock oscillation circuit has a low amplification factor to reduce current dissipation and is more susceptible to noise than the main system clock oscillation circuit. therefore, exercise utmost care in wiring the subsystem clock oscillation circuit. xt1 xt2 c3 c4 r v dd xt1 xt2
pd75p3018 37 dc characteristics ( t a = C40 to +85 c, v dd = 2.2 to 5.5 v) parameter symbol conditions min. typ. max. unit low-level output i ol per pin 15 ma current total of all pins 150 ma high-level input v ih1 port s 2 , 3 2 . 7 v v dd 5.5 v 0.7 v dd v dd v voltage 2.2 v v dd < 2.7 v 0.9 v dd v dd v v ih2 ports 0, 1, 6, 7, reset 2 . 7 v v dd 5.5 v 0.8 v dd v dd v 2.2 v v dd < 2.7 v 0.9 v dd v dd v v ih3 port s 4 , 5 2 . 7 v v dd 5.5 v 0.7 v dd 13 v (during n-ch open drain) 2.2 v v dd < 2.7 v 0.9 v dd 13 v v ih4 x1, xt1 v dd C 0.1 v dd v low-level input v il1 ports 2, 3, 4, 5 2 . 7 v v dd 5.5 v 0 0.3 v dd v voltage 2.2 v v dd < 2.7 v 0 0.1 v dd v v il2 ports 0, 1, 6, 7, reset 2 . 7 v v dd 5.5 v 0 0.2 v dd v 2.2 v v dd < 2.7 v 0 0.1 v dd v v il3 x1, xt1 0 0.1 v high-level output v oh sck, so/sb0, sb1, ports 2, 3, 6, 7, bp0 to 7 v dd C 0.5 v voltage i oh = C1 ma low-level output v ol1 sck, so, ports 2, 3, 4, 5, 6, 7, i ol = 15 ma 0.2 2.0 v voltage bp0 to 7 v dd = 4.5 to 5.5 v i ol = 1.6 ma 0.4 v v ol2 sb0, sb1 during n-ch open drain 0.2 v dd v pull-up resistor 3 1 k w high-level input i lih1 v i n = v dd pins other than x1, xt1 3 a leakage current i lih2 x1, xt1 20 a i lih3 v i n = 13 v ports 4, 5 (during n-ch open drain) 20 a low-level input i lil1 v i n = 0 v pins other than x1, xt1, ports 4, 5 C3 a leakage current i lil2 x1, xt1 C20 a i lil3 ports 4, 5 (during n-ch open drain) C30 a when input instruction v dd = 5.0 v C10 C27 a is executed v dd = 3.0 v C3 C8 a high-level output i loh1 v out = v dd sck, so/sb0, sb1, ports 2, 3, 6, 7 3 a leakage current i loh2 v out = 13 v ports 4, 5 (during n-ch open drain) 20 a low-level output i lol v out = 0 v C3 a leakage current internal pull-up r l1 v i n = 0 v ports 0, 1, 2, 3, 6, 7 (except p00 pin) 50 100 200 k w resistor
pd75p3018 38 dc characteristics (t a = C40 to +85 c, v dd = 2.2 to 5.5 v) parameter symbol conditions min. typ. max. unit lcd drive voltage v lcd vac0 = 0 2.2 v dd v lcd output voltage v odc i o = 5 av lcd0 = v lcd 0 0.2 v deviation note 1 v lcd1 = v lcd 2/3 (common) v lcd2 = v lcd 1/3 lcd output voltage v ods i o = 1 a 2.2 v - v lcd - v dd 0 0.2 v deviation note 1 (segment) supply current note 2 i dd1 6.0 mhz note 3 v dd = 5.0 v 10 % note 4 3.7 11.0 ma crystal v dd = 3.0 v 10 % note 5 0.73 2.2 ma i dd2 oscillation halt v dd = 5.0 v 10 % 0.92 2.6 ma c1 = c2 = 22 pf mode v dd = 3.0 v 10 % 0.30 0.9 ma i dd1 4.19 mhz note 3 v dd = 5.0 v 10 % note 4 2.7 8.0 ma crystal v dd = 3.0 v 10 % note 5 0.57 1.7 ma i dd2 oscillation halt v dd = 5.0 v 10 % 0.90 2.5 ma c1 = c2 = 22 pf mode v dd = 3.0 v 10 % 0.28 0.8 ma i dd3 32.768 low- v dd = 3.0 v 10 % 42 126 a khz note 6 voltage v dd = 2.5 v 10 % 37 110 a crystal mode note 7 v dd = 3.0 v, t a = 25 c 42 84 a oscillation low power dissipation mode note 8 i dd4 halt low- v dd = 3.0 v 10 % 8.5 25 a mode voltage v dd = 2.5 v 10 % 5.8 17 a mode note 7 v dd = 3.0 v, t a = 25 c 8.5 17 a low power dissipation mode note 8 i dd5 xt1 = 0 v note 9 v dd = 5.0 v 10 % 0.05 10 a stop mode v dd = 3.0 v 10 % 0.02 5 a t a = 25 c 0.02 3 a notes 1. voltage deviation is the difference between the ideal values (v lcdn ; n = 0, 1, 2) of the segment and common outputs and the output voltage. 2. the current flowing through the internal pull-up resistor is not included. 3. including the case when the subsystem clock oscillates. 4. when the device operates in high-speed mode with the processor clock control register (pcc) set to 0011. 5. when the device operates in low-speed mode with pcc set to 0000. 6. when the device operates on the subsystem clock, with the system clock control register (scc) set to 1001 and oscillation of the main system clock stopped. 7. when the sub-oscillation control register (sos) is set to 0000. 8. when the sos is set to 0010. 9. when the sos is set to 0011. v dd = 3.0 v 10 % 39 117 a v dd = 3.0 v, t a = 25 c 39 78 a v dd = 3.0 v 10 % 3.5 12 a v dd = 3.0 v, t a = 25 c 3.5 7 a
pd75p3018 39 ac characteristics (t a = C40 to +85 c, v dd = 2.2 to 5.5 v) parameter symbol conditions min. typ. max. unit cpu clock cycle time note 1 t cy operation when ceramic v dd = 2.7 to 5.5 v 0.67 64 s (minimum instruction with or crystal is used v dd = 2.2 to 5.5 v 0.85 64 s execution time main system when external v dd = 2.7 to 5.5 v 0.67 64 s = 1 machine cycle) clock clock is used 0.95 64 s operation with subsystem 114 122 125 s clock ti0, ti1, ti2 input frequency f ti v dd = 2.7 to 5.5 v 0 1 mhz 0 275 khz ti0, ti1, ti2 high-/low-level t tih , t til v dd = 2.7 to 5.5 v 0.48 s widths 1.8 s interrupt input high-/low-level t inth , t intl int0 note 2 s widths int1, 2, 4 10 s kr0-7 10 s reset low-level width t rsl 10 s notes 1. the cycle time of the cpu clock ( f ) is determined by the oscillation frequency of the connected resonator (and external clock), the system clock control register (scc), and processor clock control register (pcc). the figure on the right shows the supply voltage v dd vs. cycle time t cy characteristics when the device operates with the main system clock. 2. 2t cy or 128/f x depending on the setting of the interrupt mode register (im0). remark the shaded portion indicates the range when the external clock is used. operation guaranteed range supply voltage v dd [v] 0123456 0.5 1 2 3 4 5 6 60 64 70 cycle time t cy [ s] t cy vs v dd (with main system clock)
pd75p3018 40 serial transfer operation 2-wire and 3-wire serial i/o modes (sc k ... internal clock output): ( t a = C40 to +85 c, v dd = 2.2 to 5.5 v) parameter symbol conditions min. typ. max. unit sck cycle time t kcy1 v dd = 2.7 to 5.5 v 1300 ns 3800 ns sck high-/low-level widths t kl 1 , t kh1 v dd = 2.7 to 5.5 v t kcy 1 /2C50 ns t kcy 1 /2C150 ns si note 1 setup time (to sc k - ) t sik1 v dd = 2.7 to 5.5 v 150 ns 500 n s si note 1 hold time (from sc k - ) t ksi1 v dd = 2.7 to 5.5 v 400 ns 600 n s sck ? ? s o note 1 output t kso1 r l = 1 k w , note 2 v dd = 2.7 to 5.5 v 0 250 ns dela y time c l = 100 pf 0 1000 ns 2-wire and 3-wire serial i/o modes (sck ... external clock input): (t a = C40 to +85 c, v dd = 2.2 to 5.5 v) parameter symbol conditions min. typ. max. unit sck cycle time t kcy2 v dd = 2.7 to 5.5 v 800 ns 3200 ns sck high-/low-level widths t kl 2 , t kh2 v dd = 2.7 to 5.5 v 400 ns 1600 ns si note 1 setup time (to sc k - ) t sik2 v dd = 2.7 to 5.5 v 100 ns 150 n s si note 1 hold time (from sc k - ) t ksi2 v dd = 2.7 to 5.5 v 400 ns 600 n s sck ? ? s o note 1 output t kso2 r l = 1 k w , note 2 v dd = 2.7 to 5.5 v 0 300 ns dela y time c l = 100 pf 0 1000 ns note s 1 . in 2-wire serial i/o mode, read sb0 or sb1 instead. 2 . r l and c l respectively indicate the load resistance and load capacitance of the so output line.
pd75p3018 41 sbi mode (sck ... internal clock output (master)): (t a = C40 to +85 c, v dd = 2.2 to 5.5 v) parameter symbol conditions min. typ. max. unit sck cycle time t kcy3 v dd = 2.7 to 5.5 v 1300 ns 3800 ns sck high-/low-level widths t kl 3 , t kh3 v dd = 2.7 to 5.5 v t kcy 3 /2C50 ns t kcy 3 /2C150 ns sb0, 1 setup time t sik3 v dd = 2.7 to 5.5 v 150 ns (to sck - ) 500 n s sb0, 1 hold time (from sc k - ) t ksi3 t kcy 3 /2 n s sc k ? ? sb0, 1 output t kso3 r l = 1 k w , note v dd = 2.7 to 5.5 v 0 250 ns dela y time c l = 100 pf 0 1000 ns sck - ? sb0, 1 ? t ksb t kcy3 ns sb0, 1 ? ? sc k ? t sbk t kcy3 ns sb0, 1 low-level width t sbl t kcy3 ns sb0, 1 high-level width t sbh t kcy3 ns sbi mode (sck ... external clock input (slave)): (t a = C40 to +85 c, v dd = 2.2 to 5.5 v) parameter symbol conditions min. typ. max. unit sck cycle time t kcy4 v dd = 2.7 to 5.5 v 800 ns 3200 ns sck high-/low-level widths t kl 4 , t kh4 v dd = 2.7 to 5.5 v 400 ns 1600 ns sb0, 1 setup time t sik4 v dd = 2.7 to 5.5 v 100 ns (to sck - ) 150 n s sb0, 1 hold time (from sc k - ) t ksi4 t kcy 4 /2 n s sc k ? ? sb0, 1 output t kso4 r l = 1 k w , note v dd = 2.7 to 5.5 v 0 300 ns dela y time c l = 100 pf 0 1000 ns sck - ? sb0, 1 ? t ksb t kcy4 ns sb0, 1 ? ? sc k ? t sbk t kcy4 ns sb0, 1 low-level width t sbl t kcy4 ns sb0, 1 high-level width t sbh t kcy4 ns not e r l and c l respectively indicate the load resistance and load capacitance of the sb0, 1 output line.
pd75p3018 42 ac timing test points (except x1 and xt1 inputs) clock timing ti0, ti1, ti2 timing test points v ih v il v oh v ol xt1 input 1/f xt t xtl t xth v dd ?.1 v 0.1 v x1 input 1/f x t xl t xh v dd ?.1 v 0.1 v ti0, ti1, ti2 1/f ti t til t tih
pd75p3018 43 serial transfer timing 3-wire serial i/o mode 2-wire serial i/o mode sck t kcy1,2 t kl1,2 t kh1,2 t sik1,2 t ksi1,2 si t kso1,2 input data output data so sck t kcy1,2 t kl1,2 t kh1,2 t sik1,2 t ksi1,2 t kso1,2 sb0, 1
pd75p3018 44 serial transfer timing bus release signal transfer command signal transfer interrupt input timing reset input timing t ksb t sbl t sbh t sbk t kcy3, 4 t kl3, 4 t kh3, 4 t sik3, 4 t ksi3, 4 t kso3, 4 sck sb0, 1 t kcy3, 4 t kl3, 4 t kh3, 4 t ksb t sbk t sik3, 4 t kso3, 4 sb0, 1 sck t ksi3, 4 t intl t inth int0,1,2,4 kr0-7 t rsl reset
pd75p3018 45 data retention characteristics of data memory in stop mode and at low supply voltage (t a = C40 to +85 c) parameter symbol conditions min. typ. max. unit release signal setup time t srel 0 s oscillation stabilization t wait released by reset 2 15 /f x ms wait time note 1 released by interrupt request note 2 ms notes 1. the oscillation stabilization wait time is the time during which the cpu stops operating to prevent unstable operation when oscillation is started. 2. set by the basic interval timer mode register (btm). (refer to the table below.) wait time btm3 btm2 btm1 btm0 f x = 4.19 mhz f x = 6.0 mhz C0002 20 /f x (approx. 250 ms) 2 20 /f x (approx. 175 ms) C0112 17 /f x (approx. 31.3 ms) 2 17 /f x (approx. 21.8 ms) C1012 15 /f x (approx. 7.81 ms) 2 15 /f x (approx. 5.46 ms) C1112 13 /f x (approx. 1.95 ms) 2 13 /f x (approx. 1.37 ms) data retention timing (when stop mode released by reset) data retention timing (standby release signal: when stop mode released by interrupt signal) stop mode v dd operation mode internal reset operation oscillation stabilization wait time data retention mode t srel t wait stop instruction execution reset v dddr stop mode v dd operation mode oscillation stabilization wait time data retention mode t srel t wait stop instruction execution standby release signal (interrupt request) v dddr
pd75p3018 46 dc programming characteristics (t a = 25 5 c, v dd = 6.0 0.25 v, v pp = 12.5 0.3 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit input voltage high v ih1 except x1, x2 0.7 v dd v dd v v ih2 x1, x2 v dd C 0.5 v dd v input voltage low v il1 except x1, x2 0 0.3 v dd v v il2 x1, x2 0 0.4 v input leakage current i li v in = v il or v ih 10 a output voltage high v oh i oh = C1 ma v dd C 1.0 v output voltage low v ol i ol = 1.6 ma 0.4 v v dd supply current i dd 30 ma v pp supply current i pp md0 = v i l , md1 = v ih 30 ma caution s 1 . ensure that v pp does not exceed +13.5 v including overshoot. 2 . v dd must be applied before v p p , and cut after v p p . ac programming characteristics (t a = 25 5 c, v dd = 6.0 0.25 v, v pp = 12.5 0.3 v, v ss = 0 v) parameter symbol note 1 conditions min. typ. max. unit address setup time note 2 (to md 0 ? ) t as t as 2 s md1 setup time (to md 0 ? ) t m1s t oes 2 s data setup time (to md 0 ? ) t ds t ds 2 s address hold time note 2 (from md0 - ) t ah t ah 2 s data hold time (from md0 - ) t dh t dh 2 s md0 - ? data output float delay time t df t df 0 130 n s v pp setup time (to md3 - ) t vps t vps 2 s v dd setup time (to md 3 - ) t vds t vcs 2 s initial program pulse width t pw t pw 0.95 1.0 1.05 m s additional program pulse width t opw t opw 0.95 21.0 m s md0 setup time (to md 1 - ) t m0s t ces 2 s md0 ? ? data output delay time t dv t dv md0 = md1 = v il 1 s md1 hold time (from md0 - ) t m1h t oeh 2 s md1 recovery time (from md 0 ? ) t m1r t or 2 s program counter reset time t pcr 1 0 s x1 input high-/low-level width t xh , t xl 0.125 s x1 input frequency f x 4.19 mhz initial mode setting time t i 2 s md3 setup time (to md 1 - ) t m3s 2 s md3 hold time (from md1 ? ) t m3h 2 s md3 setup time (to md 0 ? ) t m3sr program memory read 2 s data output delay time from address note 2 t dad t acc program memory read 2 s data output hold time from address note 2 t had t oh program memory read 0 130 s md3 hold time (from md0 - ) t m3hr program memory read 2 s md3 ? ? data output float delay time t dfr program memory read 2 s note s 1 . symbol of corresponding pd27c256a 2 . the internal address signal is incremented by 1 on the 4th rise of the x1 input, and is not connected to a pin. t m1h + t m1r 3 50 s
pd75p3018 47 program memory write timing program memory read timing v pp v dd v dd +1 v dd x1 p40-p43 p50-p53 md0 md1 md2 md3 v dd v pp data output data output t vps t vds t xh t xl t dad t had t dv t dfr t m3hr t i t pcr t m3sr v pp v dd v dd +1 v dd x1 p40-p43 p50-p53 md0 md1 md2 md3 v pp v dd data input data output data input data input t vps t vds t xh t xl t i t ds t oh t pw t dv t df t m1r t m0s t ds t dh t opw t ah t as t m1s t m1h t pcr t m3s t m3h
pd75p3018 48 10. package drawings a m f b 60 61 40 k l 80 pin plastic qfp ( 14) 80 1 21 20 41 g d c detail of lead end s q p m i h j 5 5 n s80gc-65-3b9-3 item millimeters inches a b c d f g h i j k l 17.2 0.4 14.0 0.2 0.8 0.30 0.10 0.13 14.0 0.2 0.677 0.016 0.031 0.031 0.005 0.026 (t.p.) 0.551 note m n 0.10 0.15 1.6 0.2 0.65 (t.p.) 0.004 0.006 +0.004 ?.003 each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. 0.063 0.008 0.012 0.551 0.8 0.2 0.031 p 2.7 0.106 0.677 0.016 17.2 0.4 0.8 +0.009 ?.008 q 0.1 0.1 0.004 0.004 s 3.0 max. 0.119 max. +0.10 ?.05 +0.009 ?.008 +0.004 ?.005 +0.009 ?.008
pd75p3018 49 80 pin plastic tqfp (fine pitch) ( 12) item millimeters inches i j 0.5 (t.p.) 0.10 0.004 0.020 (t.p.) a note each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. s a 14.0 0.2 0.551 +0.009 ?.008 b 12.0 0.2 0.472 +0.009 ?.008 c 12.0 0.2 0.472 +0.009 ?.008 d 14.0 0.2 0.551 +0.009 ?.008 f g 1.25 1.25 0.049 0.049 h 0.22 0.009 0.002 p80gk-50-be9-4 s 1.27 max. 0.050 max. k 1.0 0.2 0.039 +0.009 ?.008 l 0.5 0.2 0.020 +0.008 ?.009 m 0.145 0.006 0.002 n 0.10 0.004 p 1.05 0.041 q 0.05 0.05 0.002 0.002 r5 5 5 5 +0.05 ?.04 +0.055 ?.045 b c d j h i g f p n l k m q r detail of lead end m 61 60 41 40 21 20 1 80
pd75p3018 50 11. recommended soldering conditions solder the pd75p3018 under the following recommended conditions. for the details on the recommended soldering conditions, refer to information document semiconductor device mounting technology manual (c10535e) . for the soldering methods and conditions other than those recommended, consult nec. table 11-1. soldering conditions of surface mount type (1) pd75p3018gc-3b9: 80-pin plastic qfp (14 14 mm) soldering method soldering conditions symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (210 c min.), ir35-00-3 number of times: 3 max. vps package peak temperature: 215 c, time: 40 seconds max. (200 c min.), vp15-00-3 number of times: 3 max. wave soldering solder temperature: 260 c max., time: 10 seconds max., ws60-00-1 number of times: 1 preheating temperature: 120 c max. (package surface temperature) pin partial heating pin temperature: 300 c max., time: 3 seconds max. (per side of device) caution do not use two or more soldering methods in combination (except the pin partial heating method). (2) pd75p3018gk-be9: 80-pin plastic tqfp (fine pitch) (12 12 mm) soldering method soldering conditions symbol infrared reflow ir35-107-2 vps vp15-107-2 wave soldering ws60-107-1 pin partial heating note the number of days for storage after the dry pack has been opened. the storage conditions are 25 c, 65 % rh max. caution do not use two or more soldering methods in combination (except the pin partial heating method). package peak temperature: 235 c, time: 30 seconds max. (210 c min.), number of times: 2 max., exposure limit: 7 days note (after that, prebaking is necessary at 125 c for 10 hours.) package peak temperature: 215 c, time: 40 seconds max. (200 c min.), number of times: 2 max., exposure limit: 7 days note (after that, prebaking is necessary at 125 c for 10 hours.) solder temperature: 260 c max., time: 10 seconds max., number of times: 1, preheating temperature: 120 c max. (package surface temperature) exposure limit: 7 days note (after that, prebaking is necessary at 125 c for 10 hours.) pin temperature: 300 c max., time: 3 seconds max. (per side of device) *
pd75p3018 51 appendix a pd75316b, 753017 and 75p3018 function list parameter pd75316b pd753017 pd75p3018 program memory mask rom mask rom one-time prom 0000h-3f7fh 0000h-5fffh 0000h-7fffh (16256 8 bits) (24576 8 bits) (32768 8 bits) data memory 000h-3ffh (1024 4 bits) cpu 75x standard 75xl cpu instruction when main system 0.95, 1.91, or 15.3 s ? 0.95, 1.91, 3.81, or 15.3 s (at 4.19 mhz operation) execution time clock is selected (at 4.19 mhz operation) ? 0.67, 1.33, 2.67, or 10.7 s (at 6.0 mhz operation) when subsystem 122 s (at 32.768 khz operation) clock is selected pin connection 29 to 32 p40 to p43 p40/d0 to p43/d3 34 to 37 p50 to p53 p50/d4 to p53/d7 44 p12/int2 p12/int2/ti1/ti2 47 p21 p21/pto1 48 p22/pcl p22/pcl/pto2 50 to 53 p30 to p33 p30/md0 to p33/md3 57 ic v pp stack sbs register none sbs.3 = 1; mk i mode selection sbs.3 = 0; mk ii mode selection stack area 000h-0ffh n00h-nffh (n = 0-3) subroutine call instruction 2-byte stack mk i mode: 2-byte stack stack operation mk ii mode: 3-byte stack instruction bra !addr1 unavailable mk i mode: unavailable calla !addr1 mk ii mode: available movt xa, @bcde available movt xa, @bcxa br bcde br bcxa call !addr 3 machine cycles mk i mode: 3 machine cycles, mk ii mode: 4 machine cycles callf !faddr 2 machine cycles mk i mode: 2 machine cycles, mk ii mode: 3 machine cycles mask option yes none timer 3 channels: 5 channels: ? basic interval timer ? basic interval timer/watchdog timer: 1 channel : 1 channel ? 8-bit timer/event counter: 3 channels ? 8-bit timer/event counter (can be used as 16-bit timer/event counter) : 1 channel ? watch timer: 1 channel ? watch timer: 1 channel
pd75p3018 52 parameter pd75316b pd753017 pd75p3018 clock output (pcl) f , 524, 262, 65.5 khz ? f , 524, 262, 65.5 khz (main system clock: (main system clock: at 4.19 mhz operation) at 4.19 mhz operation) ? f , 750, 375, 93.8 khz (main system clock: at 6.0 mhz operation) buz output (buz) 2 khz ? 2, 4, 32 khz (main system clock: (main system clock: at 4.19 mhz operation or at 4.19 mhz operation) subsystem clock: at 32.768 khz operation) ? 2.86, 5.72, 45.8 khz (main system clock: at 6.0 mhz operation) serial interface 3 modes are available ? 3-wire serial i/o mode ... msb/lsb can be selected for transfer top bit ? 2-wire serial i/o mode ? sbi mode sos register feedback resistor cut flag none provided (sos.0) sub-oscillator current none provided cut flag (sos.1) register bank selection register (rbs) none yes standby release by int0 no yes vectored interrupt external: 3, internal: 3 external: 3, internal: 5 supply voltage v dd = 2.0 to 6.0 v v dd = 2.2 to 5.5 v operating ambient temperature t a = C40 to +85 c package ? 80-pin plastic tqfp (fine pitch) (12 x 12 mm) ? 80-pin plastic qfp (14 x 14 mm) *
pd75p3018 53 appendix b development tools the following development tools have been provided for system development using the pd75p3018. in the 75xl series, the relocatable assembler common to series is used in combination with the device file of each type. ra75x relocatable assembler host machine part no. (name) os supply medium pc-9800 series ms-dos tm 3.5" 2hd s5a13ra75x ver.3.30 to 5" 2hd s5a10ra75x ver.6.2 note ibm pc/at tm refer to "os for 3.5" 2hc s7b13ra75x or compatible ibm pcs" 5" 2hc s7b10ra75x device file host machine part no. (name) os supply medium pc-9800 series ms-dos 3.5" 2hd s5a13df753017 ver.3.30 to 5" 2hd s5a10df753017 ver.6.2 note ibm pc/at refer to "os for 3.5" 2hc s7b13df753017 or compatible ibm pcs" 5" 2hc s7b10df753017 note ver. 5.00 or later includes a task swapping function, but this software is not able to use that function. remark operation of the assembler and device file is guaranteed only when using the host machine and os described above. * *
pd75p3018 54 prom write tools hardware pg-1500 this is a prom programmer that can program single-chip microcontroller with prom in stand alone mode or under control of host machine when connected with supplied accessory board and optional programmer adapter. it can also program typical proms in capacities ranging from 256 k to 4 m bits. pa-75p316bgc this is a prom programmer adapter for the pd75p316bgc and pd75p3018gc. it can be used when connected to a pg-1500. pa-75p316bgk this is a prom programmer adapter for the pd75p316bgk and pd75p3018gk. it can be used when connected to a pg-1500. software pg-1500 controller connects pg-1500 to host machine with serial and parallel interface and controls pg-1500 on host machine. host machine part no. (name) os supply medium pc-9800 series ms-dos 3.5" 2hd s5a13pg1500 ver.3.30 to 5" 2hd s5a10pg1500 ver.6.2 note ibm pc/at refer to "os for 3.5" 2hd s7b13pg1500 or compatible ibm pcs" 5" 2hc s7b10pg1500 note ver. 5.00 or later includes a task swapping function, but this software is not able to use that function. remark operation of the pg-1500 controller is guaranteed only when using the host machine and os described above. * *
pd75p3018 55 debugging tools in-circuit emulators (ie-75000-r and ie-75001-r) are provided as program debugging tools for the pd75p3018. various system configurations using these in-circuit emulators are listed below. hardware ie-75000-r note 1 the ie-75000-r is an in-circuit emulator to be used for hardware and software debugging during development of application systems using the 75x or 75xl series products. for development of the pd75p3018, the ie-75000-r is used with optional emulation board (ie- 75300-r-em) and emulation probe (ep-753018gc-r or ep-753018gk-r). highly efficient debugging can be performed when connected to host machine and prom programmer. the ie-75000-r includes a connected emulation board (ie-75000-r-em). ie-75001-r the ie-75001-r is an in-circuit emulator to be used for hardware and software debugging during development of application systems using the 75x or 75xl series products. the ie-75001-r is used with optional emulation board (ie-75300-r-em) and emulation probe (ep-753018gc-r or ep-753018gk-r). highly efficient debugging can be performed when connected to host machine and prom programmer. ie-75300-r-em note 2 this is an emulation board for evaluating application systems using the pd75p3018. it is used in combination with the ie-75000-r or ie-75001-r. ep-753018gc-r this is an emulation probe for the pd75p3018gc. when being used, it is connected with the ie-75000-r or ie-75001-r and the ie-75300-r-em. ev-9200gc-80 it includes a 80-pin conversion socket (ev-9200gc-80) to facilitate connections with target system. ep-753018gk-r this is an emulation probe for the pd75p3018gk. when being used, it is connected with the ie-75000-r or ie-75001-r and the ie-75300-r-em. ev-9500gk-80 it includes a 80-pin conversion adapter (ev-9500gk-80) to facilitate connections with target system. software ie control program this program can control the ie-75000-r or ie-75001-r on a host machine when connected to the ie-75000-r or ie-75001-r via an rs-232-c or centronics interface. host machine part no. (name) os supply medium pc-9800 series ms-dos 3.5" 2hd s5a13ie75x ver.3.30 to 5" 2hd s5a10ie75x ver.6.2 note 3 ibm pc/at refer to "os for 3.5" 2hc s7b13ie75x or compatible ibm pcs" 5" 2hc s7b10ie75x notes 1. this is a maintenance product. 2. the ie-75300-r-em is sold separately. 3. ver. 5.00 or later includes a task swapping function, but this software is not able to use that function. remark operation of the ie control program is guaranteed only when using the host machine and os described above. *
pd75p3018 56 os for ibm pcs the following operating systems for the ibm pc are supported. os version pc dos tm ver.3.1 to ver.6.3 ms-dos ver.5.0 to ver.6.22 5.0/v to 6.2/v ibm dos tm j5.02/v caution ver. 5.0 or later includes a task swapping function, but this software is not able to use that function. * * *
pd75p3018 57 appendix c related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. device related documents document no. document name japanese english pd753012, 753016, 753017 data sheet ic-9016 u10140e pd75p3018 data sheet u10956j u10956e (this document) pd753017 user's manual u11282j ieu-1425 pd753017 instruction table iem-5598 75xl series selection guide u10453j u10453e development tool related documents document no. document name japanese english ie-75000-r/ie-75001-r user's manual eeu-846 eeu-1416 hardware ie-75300-r-em user's manual u11354j eeu-1493 ep-753017gc/gk-r user's manual eeu-967 ieu-1495 pg-1500 user's manual eeu-651 eeu-1335 ra75x assembler package operation eeu-731 eeu-1346 user's manual language eeu-730 eeu-1363 software pg-1500 controller user's manual pc-9800 series eeu-704 eeu-1291 (ms-dos) base ibm pc series eeu-5008 u10540e (pc dos) base other related documents document no. document name japanese english ic package manual c10943x semiconductor device mounting technology manual c10535j c10535e quality grades on nec semiconductor devices iei-620 iei-1209 nec semiconductor device reliability/quality control system c10983j c10983e electrostatic discharge (esd) test mem-539 guide to quality assurance for semiconductor devices mei-603 mei-1202 guide for products related to microcomputer: other companies mei-604 caution the above related documents are subject to change without notice. for design purpose, etc., be sure to use the latest documents. *
pd75p3018 58 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd75p3018 59 nec electronics inc. (u.s.) mountain view, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby sweden tel: 8-63 80 820 fax: 8-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 3
pd75p3018 60 ms-dos is a trademark of microsoft corporation. ibm dos, pc dos, and pc/at are trademarks of international business machines corporation. the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5


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